Multicore SoC TestChip For Mobile Application


Test Chips For Mobile Processor Application


Silicon Engineering / Semiconductor






Mobile Processor

PROJECT DESCRIPTION : Multi-layer, Multi-core Soc

  • This test chips mainly targets for snapdragon processor.
  • JTAG are nothing but the PAD’s which are sitting outside of the test chip. (basically on the boundary of the test chip)
  • For every test chips, the initial verification will be the functionality check of the JTAG.
  • The JTAG ID codes are different for different test chips.
  • The test procedure which ran on silicon to get the yield are nothing but the “bit files” generated by the GLS team.
  • Based on the silicon debug, any changes in the bit file (generated from GLS) prompts the changes in the DV test files(means file)

ROLE : Verification of following is within scope for Blueberry.

  • Connectivity checks between the blocks present in the test chip.
  • Ensure JTAG (Joint test action group) interface are proper with respect to all the blocks present in the design.
  • Create or update the verification suite based on the feature enhancements if needed.
  • Make sure all the test procedures, which are targeted for silicon along with basic functionality are verified along with coverage closure.

HIGHLIGHTS : Reduced time2market by – proactivity meeting the milestone targeted for tape outs in order to achieve better yield of the test chip silicon.


  • JTAG scan chain analysis/connectivity of all the blocks.
  • Data integrity check w.r.t different blocks present in the test chip Soc
  • Modify the test procedure based on the silicon debug to ensure better yield.
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