Subsystem Verification of Image Compression Block


Image Processing SoC


Silicon Engineering / Semiconductor


Synopsys VCS and Verdi, Python, Perl


Image Compression for SoC

PROJECT DESCRIPTION : Turing Subsystem: It’s a part of SoC, used for image compression.

  • This chip is used in server as a result cache level is increased and external slaves are very large memories to store the data.
  • CCN was used so that there is no bus constraints.
  • CCN works on Round Robin node and has different slaves connected to different nodes
  • Performance limitation => Speculation access from snoop control unit/cluster was coming out as Zero address for core-1, which was not accepted as per the design intent

ROLE : Verification of following is within scope for Blueberry


  • Integration of Dynamic ACC Override
  • Integration of Unrepair feature for memory redundancy block
  • Removal of Streamer, VMA blocks


  • Verifying all the features of SS for Q2 and Q3 mile stone
  • Interrupt generation verification for removal of streamer block
  • Unrepair feature verification for memory redundancy
  • Verifying Dynamic ACC Override Feature.
  • Formal connectivity checks


  • Updating the existing TB to verify added features and cleaning up Regression Failures.


  • Completed Q2 mile stone.
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