SoC Verification for Navigation based Application


SoC Verification for Navigation based Application


Silicon Engineering / Automotive


Questasim, GCC


System Verilog, C, shell

PROJECT DESCRIPTION : GNSS based, dual-core (Esi-RISC)

This SoC is developed with an intent to use in navigation based applications.

It had multicore processor (dual), AHB fabric which connects to memories, AHB to APB bridges, SMIC, SPI FLASH and APB instances which connects to peripherals such as GPIO, SPI, UART, I2C, CAN etc. 

In this project, I was fortunate to get my hands on most of the modules to verify various features as per requirements.

For all the verification purpose I used questasim and GCC. UVM and C were used.

To mention a few,

  • Verified UART0/1/2 instances for internal loop backs (to aid in BIST), various Baudrates, word sizes, parity, stop, start bits, interrupts (TXAE, RXAF, TXE, RXF).
  • Verified SPI0/1 instances for internal loop backs, various frequencies, multi master/slave configurations, word sizes, interrupts.
  • Verified GPIO0/1/2/3/4/5/6 instances for Input/Output operations, interrupts (pos/neg level/edge).
  • Verified I2C0/1 instances for 7bit/10bit addressing modes, word sizes, various frequencies, interrupts.
  • Verified CAN0/1 instances for internal loop backs.
  • Verified SPI FLASH for serial, dual and quad mode operations.
  • Verified SMIC for asyn RAM model operation with various word sizes, read/write wait states.
  • Verified SGDMA access of all memories and peripherals through various channels for different word sizes.
  • Verified ECC enabled RAM by modelling exact ECC model and by efficient use of constrained random stimulus.
  • Verified 1st and 2nd I/O muxing using primitive gates such as pass transistors.
  • Developed interface monitors for UART, SPI FLASH and SMIC interfaces to get respective bandwidth figures and for self checking.
  • Developed AHB level monitor for system level performance measurements (bandwidth calculation).
  • Handled Jenkins, in order to automate daily regressions and to report the results.

ROLE : Verification (pre-silicon validation)

  • APB0/1 and AHB level peripheral’s verification
  • Synchronization between CPUs
  • Peripheral map checking
  • ECC block, Loop back features verification
  • Performance measurement at interface level and AHB level
  • Handled Jenkins

HIGHLIGHTS : Developed scripts to perform local regressions and to extract needful info.


  • Cache coherency issues while accessing cache enabled regions
  • Verification of ECC and GPIO’s through controlled randomization
  • Accessing SPI flash devices
  • Setting up Jenkins and managing available resources efficiently
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