SOC For Data-Flow Intensive Application For AI Application


SoC for AI application


Silicon Engineering / Semiconductor


VCS, Python, GCC


Artificial Intelligence SoC

PROJECT DESCRIPTION : Multi-master, Multi-core (ARM A53)

  • This chip is used in server as a result cache level is increased and external slaves are very large memories to store the data.
  • CCN was used so that there is no bus constraints.
  • CCN works on Round Robin node and has different slaves connected to different nodes
  • Performance limitation => Speculation access from snoop control unit/cluster was coming out as Zero address for core-1, which was not accepted as per the design intent

ROLE : Verification of following is within scope for Blueberry


  • Integration of PSOC (peripheral SoC)
  • Integration SRAM.


  • PLL verification
  • Coherency between A53 cores
  • Early Bresponse to A53 (this increases the speed)
  • Address map testing for NIC 500 (okay, slave error, decode error)

Challenges :

  • Cache analysis of Multi-core & Multi-Master
  • Data flow analysis in proprietary MESH network interconnect


  • Reduced time2debug by – Proactively developing debug assist-automation of CPU subsystem
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