SoC For 5G Application


SoC For Video Application


Hardware Design / Semiconductor


VCS, Questa Sim


RF IF SoC for 5G

PROJECT DESCRIPTION : Multi-master, Multi-core (ARM A53)

  • This chip is used in server as a result cache level is increased and external slaves are very large memories to store the data.
  • CCN was used so that there is no bus constraints.
  • CCN works on Round Robin node and has different slaves connected to different nodes
  • Performance limitation => Speculation access from snoop control unit/cluster was coming out as Zero address for core-1, which was not accepted as per the design intent.

ROLE : Verification of AM controller block with

  • Read/write test
  • Multiple host access test
  • FIFO full test
  • Timeout check
  • Maximum power test


  • SBFC Parser data padding
  • C2C to LVDS data transfer without loss.


  • Coverage improvement from 81% to 97%.
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