Signal Integrity For High Speed IO Of LPDDR4
PROJECT DESCRIPTION : DSPG-ASIC – 7nm Rhea LPDDR4 & 4x, IO validation
ROLE : Verification of following is within scope for Blueberry
- LPDDR4 and 4x
- TM NAND IO Acceptance.
- Simulation of LPDDR4 at 4266 Mbps in System Level simulation
- Simulation of LPDDR4x at 4266 Mbps in System Level simulation.
- Simulation of NAND IO at 2400 Mbps in System Level simulation
- Simulation of LPDDR4,4x and NAND IO at system level with top speed.
- Validation of NAND IO net-list received from ASIC IO Team.
- Connecting the signals on PCB with shorter lengths by optimizing placements.
- Signal Integrity for LPDDR4 and NAND IO is achieved with good margins at top speed in system level simulations.