Post Silicon Validation of Navigation Chip


Post Silicon Validation Of SoC


Hardware Design / Automotive


Eclipse, GCC, Python IDE


C, Python
PROJECT DESCRIPTION : GNSS based, dual-core (Esi-RISC)
  • It was exciting to work on the post-silicon phase of the DUT on which pre-silicon verification was performed.
  • The setup had a huge PCB board on which 2 FPGA’s (A & B) and base board were sitting.
  • The FPGA’s had master/slave logic for all the peripheral controllers, I/O Muxes available inside the DUT. Python was the only way to talk to these FPGA’s.
  • Most of the verification phase testcases were ported as they are with additional logic added wherever is needed.
  • The difficult part was, validating peripheral controllers with limited visibility to internal signals.
  • Observing the signals (data + control) on the oscilloscope to make sure what is being driven from/to DUT is reflected on the IO pins with minimum loss.
  • Identifying possible root cause of any issue which could be from defective DUT and/or Package and/or FPGA and/or improper Connections and/or incorrect configurations and/or compatibility issues with FPGA’s master/slave with DUT’s slave/master etc.

ROLE : Validation (post-silicon validation)

  • APB0/1 and AHB level peripheral’s validation
  • Synchronization between base board (SoC) and FPGA’s (A & B)
  • Validating frequencies and data paths of peripheral’s using oscilloscope.


  • Limited visibility to internal signals (wires) of DUT
  • Synchronization between python (FPGA) and C (SoC)
  • Identifying and categorizing DUT’s genuine issues and Package/connectivity issues
  • Power supply and current consumption monitoring
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