Multicore SoC For High Performance Flash Memory Controller Verification


SoC for High Performance Flash Memory Application


Silicon Engineering / Consumer


Cadence Ncsim


SSD Controller SoC – Memory Application

PROJECT DESCRIPTION : High performance flash memory controller ASIC that supports the SSD device. ARC HS multicore architecture & incorporates several significant HW automation Ips to increase both sequential & random performance.

  • This chip is used in server as a result cache level is increased and external slaves are very large memories to store the data.
  • CCN was used so that there is no bus constraints.
  • CCN works on Round Robin node and has different slaves connected to different nodes
  • Performance limitation => Speculation access from snoop control unit/cluster was coming out as Zero address for core-1, which was not accepted as per the design intent

ROLE : Verification of full chip level

  • ASIC, FPGA & GLS Verification
  • Clock management controller: configuration & verification of soc clocks, domain clocks
  • Frequency Monitor block : Core is to measure on-chip oscillator frequency during the calibration process.
  • Verification of Special function register(SFR): SFR AON controls the AON analog parts, SFR Top controls the PLLs and other elements that are in top domain
  • Worked on Preamble, Clock config Preamble. All the expected frequencies generated from Preamble should match to scan output frequency
  • Xprop methodology, checking x-props in design using different modes, xprop methodology is mainly used to detect the x-props in design.


  • Verification Multi-core’s(7 core) Data flow analysis, connectivity and functional checks


  • Introduced & Implemented xprop methodology, X-prop is designed to help find X-related issues at RTL and reduce the requirement for lengthy gate-level simulations.
  • Filed many bug in ASIC simulation & FPGA simulation
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