Location: Bangalore

Experience: 1-15 Years

Preferred Education

• B.Tech/M.Tech

Area of Expertise 

· Good knowledge of VLSI process and device characteristics

· Experience doing physical design targeted to the 7nm/16nm FinFet process

· Good knowledge of cell libraries’ various views and models

· Good understanding of static timing analysis (STA), EM/IR, and sign-off

· Strong hands-on experience with Chip Level / Sub-chip level floor planning, > partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, > Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks, and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification – block and chip level

· EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC, etc

· Good software and scripting skills (Python, tcl)

· Good communication skills and the ability and desire to work as part of a team

· Self-driven individual and an excellent team player

· Good communication abilities