Custom Layout Of Blocks For TestChip

NAME:

Custom Layout Of Blocks For TestChip

DOMAIN / CATEGORY:

Silicon Engineering / Semiconductor

TOOLS:

Cadence, Mentor

PROJECT DESCRIPTION : Custom Layout of blocks 12nm FinFET

SCOPE:

  • Custom Layout of design as per layout plan and instructions from SiliconLib
  • Physical Verification (DRC, LVS) and LPE extraction if needed

TARGET PROCESS : 12nm FinFET

HIGHLIGHTS :

  • Total 12 blocks
  • Highspeed SERDES
  • Low power

Complexity Overcome :

  • Tight schedule to meet MPW date
  • PD kit integration into Tools
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