Compiler Development For Speech Processing SoC

NAME:

Compiler Development for AI Chip

DOMAIN / CATEGORY:

Machine Learning & Turnkey – Software Solutions / Consumer Electronic

PROJECT DESCRIPTION : Compiler for speech processing on the SoC Board using DNN

IP Verification of VESA DSC (Display Stream Compression).

DSC is an industry wide compression standard for vedio interfaces that features low latency and visually lossless performance, DSC is currently integrated into standards used for embedded display interfaces within the mobile systems.

Encoding and decoding schemes are deployed in DSC v1.2a to provide backward compatibility with DSC v1.1. The capabilities in DSC v1.2a allows the standard to be utilized not only for mobile displays, but also for emerging high definition TVs.

Key features include

  • Native 4:2:2 and 4:2:0 coding.
  • Upto 16 bits per color.
  • High dynamic range (HDR).

Accomplishments :

  1. Verification of Decoder scheme :
    • Single frame and single PPS (Picture Parameter Set) programming using APB 3 host interface. Scope of Operation modes Ycbcr, RGB, Native 422,Native 420 and Simple 420 are covered.
    • Multi frame and single PPS programming using APB 3 host interface. Scope of Operation modes Ycbcr, RGB, Native 422,Native 420 and Simple 420 are covered.
    • Multi frame and multiple PPS programming using APB 3 as host interface. Scope of Operation modes Ycbcr, RGB, Native 422,Native 420 and Simple 420 are covered.
    • Flush and INIT based verification.
    • CTG (Confirmance Test Guidliance) testing as per industry standards of 1k,4k,8k,10k and colorbar resolution images
    • Latency analysis and verification in multi frame scenario is the major challenging role to meet the refresh rate as per the vedio interface standards.
    • Implementation of RAL based register testing to verify the values of internal control and status registers of decoder design.
  2. Verification of Encoder scheme : In progress

Solution Approach:

  • Layer 1: ONNX : We built it around the ONNX-a framework for extracting the DNN model
  • Layer 2: MLIR: We used MLIR for DAG to IR conversion of a DNN. The target dialect is the LLVM dialect.
  • Layer 3: LLVM: We import the MLIR output for further HW specific transformation that is compatible with the ARM Cortex M4 processor.
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