NAME: Custom Layout Of Blocks For TestChip DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: Cadence, Mentor PROJECT DESCRIPTION : Custom Layout of blocks 12nm FinFET SCOPE: Custom Layout of design as per layout plan and instructions from SiliconLib Physical Verification (DRC, LVS) and LPE extraction if needed TARGET PROCESS : 12nm FinFET HIGHLIGHTS : Total 12 …
NAME: Multi-Frequency Oscillator Design DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: Cadence, Mentor PROJECT DESCRIPTION : Development of Multi-frequency oscillator from Specifications to GDS-II including custom Circuit design and Layout design and Characteristic verification SCOPE: Development of Multi-frequency oscillator Specifications to GDS-II Circuit design Layout design Characteristic verification TARGET PROCESS : TSMC CRN40G ARCHITECTURE : Ensure …
NAME: Optimus HIM Sub-System DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: Git, Cadence xcelium, Simvision, APPLICATION: Flash memory and SSD devices. PROJECT DESCRIPTION : The Optimus HIM is a USB protocol host interface sub-system, used to interface UFM based SSD controller in the back-end. The UASP & BOT Protocol interfaces supported in USB sub-system. ROLE …
Subsystem Verification USB Host Interface For SSD Controller Read More »
NAME: ADC Digital VIP DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: Cadence Xcelium APPLICATION: Post processing of ADC output based on stored calibration coefficients for offset and gain correction. PROJECT DESCRIPTION : ADC digital VIP Verification This chip is used in server as a result cache level is increased and external slaves are very large …
NAME: Test Chips For Mobile Processor Application DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: VCS LANGUAGE: Shell APPLICATION: Mobile Processor PROJECT DESCRIPTION : Multi-layer, Multi-core Soc This test chips mainly targets for snapdragon processor. JTAG are nothing but the PAD’s which are sitting outside of the test chip. (basically on the boundary of the test …
NAME: DDR5/LPDDR5X Multiply IP DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: VCS, Perl APPLICATION: Applicable To All DRAM’s PROJECT DESCRIPTION : The combophy interface is an interface protocol required to transfer command and data across the DFI and between MC & PHY. Combophy applies to LPDDR5 & DDR5 ROLE : Verification of following is within scope …
NAME: SoC for High Performance Flash Memory Application DOMAIN / CATEGORY: Silicon Engineering / Consumer TOOLS: Cadence Ncsim APPLICATION: SSD Controller SoC – Memory Application PROJECT DESCRIPTION : High performance flash memory controller ASIC that supports the SSD device. ARC HS multicore architecture & incorporates several significant HW automation Ips to increase both sequential & random …
Multicore SoC For High Performance Flash Memory Controller Verification Read More »
NAME: Image Processing SoC DOMAIN / CATEGORY: Silicon Engineering / Semiconductor TOOLS: Synopsys VCS and Verdi, Python, Perl APPLICATION: Image Compression for SoC PROJECT DESCRIPTION : Turing Subsystem: It’s a part of SoC, used for image compression. This chip is used in server as a result cache level is increased and external slaves are very large …
Subsystem Verification of Image Compression Block Read More »
NAME: SoC For Video Application. DOMAIN / CATEGORY: Silicon Engineering / Consumer TOOLS: VCS APPLICATION: Video SoC PROJECT DESCRIPTION : Verification of DMA-FDU in VIDEO SOC. This chip is used in server as a result cache level is increased and external slaves are very large memories to store the data. CCN was used so that there …
NAME: CRYPTO IP For IoT DOMAIN / CATEGORY: Silicon Engineering / Industrial Automation TOOLS: VCS, Python, G APPLICATION: IoT SoC PROJECT DESCRIPTION : This soft IP implements only AES-GCM protocol and validates the complete encryption/decryption and Authentication logic ROLE : Verification of following Develop Coverage class for Encryption and Decryption Work with DE team in closure of …
